This invention relates to phase-locked loops, and more particularly relates to phase-locked loops employing delay-line oscillators.
In transferring digital data in a system from a location on one integrated circuit to a location on another integrated circuit, it is often desired to convert the digital data from parallel form to serial form. Converting the digital data from parallel form to serial form allows the data to be transferred over a single conductor. In one example, a stream of multi-bit digital data values (each having N bits) is received over N conductors at a first clock rate FIN. This data is converted into serial form and is then transmitted over a single conductor at a faster clock rate FOUT equal to N times FIN. A circuit is therefore needed to take the first clock signal of frequency FIN and generate therefrom the faster clock signal of frequency FOUT (N times FIN) so that the faster clock signal is available to serialize the data and clock the serial data onto the single conductor. A phase-locked loop (PLL) is a circuit that can perform this frequency multiplying function.
FIG. 1 (Prior Art) is a block diagram of a PLL 1. PLL 1 includes a phase detector 2, a loop filter 3, a voltage controlled oscillator (VCO) 4, and a loop divider 5. The PLL works by detecting a difference in phase between a feedback signal SOSC on line 6 and an input signal SIN on line 7 and then adjusting the frequency FOUT of VCO output signal SOUT until the phase of the feedback signal SOSC matches the phase of the input signal SIN. If the phase of feedback signal SOSC lags the phase of input signal SIN, then an error signal on line 8 supplied to VCO 4 causes VCO 4 to increase the frequency of SOUT until the phase of the feedback signal SOSC matches the phase of input signal SIN. Similarly, if the phase of feedback signal SOSC leads the phase of input signal SIN, then the error signal on line 8 causes VCO 4 to decrease the frequency of SOUT until the phase of the feedback signal SOSC matches the phase of input signal SIN. When the PLL is xe2x80x9clockedxe2x80x9d, the frequency and phase of the feedback signal SOSC will match the frequency and phase of the input signal SIN. Because loop divider 5 divides the signal SOUT by an integer value M to obtain the signal SOSC, the frequency of the signal SOUT is M times the frequency of the input signal SIN.
Accordingly it is seen that PLL 1 is usable to generate the faster serial clock in the parallel-to-serial conversion process described above. If signal SIN is the parallel data clock of frequency FIN used to supply successive multi-bit data values, and divider 5 is set to divide by the number of bits M in each such multi-bit data value, then the signal SOUT is the faster clock signal of frequency M times FIN. Signal SOUT is then usable to serialize the parallel data and clock it onto the single conductor.
Blocks 2, 3 and 4 of the PLL of FIG. 1 are, however, not made of ideal circuitry. The electrical characteristics of these blocks vary over numerous operational conditions including operating frequency, divider value M, supply voltage VDD, temperature, and process variations. PLL 1 will, for example, only xe2x80x9clockxe2x80x9d over a finite range of frequencies FOUT, given a particular value of M and a particular loop filter. Similarly, PLL 1 will only lock over a finite range of values for M, given a particular frequency FOUT and a particular loop filter. Also, PLL 1 will only lock with certain filter characteristics which yield certain dynamic loop responses, given a particular frequency FOUT and a particular value for M. A typical conventional PLL such as the PLL of FIG. 1 will not lock where FOUT varies by a factor in excess of ten, where M varies over a range from one to 256, and where the sum of all the capacitors in the loop filter have a capacitance of less than 250 picofarads.
A PLL is desired for use in a field programmable gate array (FPGA). If, for example, the PLL is used to do parallel-to-serial conversion, then the ranges of FOUT and M may vary widely from user design to user design. The ranges of FOUT and M are controlled by the user, and are generally dictated by the particular application to which the FPGA is put. It is therefore desired to provide on the FPGA a single PLL design that is usable over wider ranges of both FOUT and M than conventional PLLs, while providing all the elements of the loop filter on-chip in an economical fashion.
A phase-locked loop (PLL) circuit includes a first phase detector, a second phase detector, a divide-by-M loop divider, a programmable tapped-delay-line oscillator, and a programmable on-chip loop filter. The programmable filter is programmable to realize one of many loop filters.
In a first step, a signal output by the oscillator is fed back (via the divide-by-M loop divider) to a first input of the first phase detector. An input signal SIN to be locked to is supplied to the second input of the first phase detector. The frequency of the oscillator output signal is then decremented by changing tap selection inside the oscillator. The frequency output by the oscillator is decremented in this manner under the control of the first phase detector until the first phase detector determines that the frequency of the signal fed back via the divider is smaller than the frequency of the input signal SIN. The PLL is then xe2x80x9cfrequency lockedxe2x80x9d with respect to input signal SIN.
The tap control at which this frequency lock condition occurred, along with value M, is then used to determine which of the many loop filters will be used in a subsequent phase lock step. This determination is made, in some embodiments, by a control block of the PLL. The programmable loop filter is then controlled to realize the selected loop filter and the selected loop filter is switched into a control loop involving the second phase detector. This control loop controls the frequency output by the oscillator to achieve phase lock by varying a supply voltage VSUP supplied to the oscillator. By using the tap control information from the frequency lock step to select the loop filter, a PLL having: 1) a wide oscillator output frequency range, 2) a wide range of divider values M, and 3) a small total loop filter capacitance is achieved.
In one embodiment, the PLL can phase lock: 1) where the oscillator outputs a signal having a frequency anywhere in the range of from 20 MHz to 400 MHz, 2) where divider value M is an integer selectable in the range of from one to 256, and 3) where the sum of all capacitances in the programmable loop filter is less than 250 picofarads. Achieving the wide ranges of oscillator frequency and divider value M while at the same time keeping the total loop filter capacitance under 250 picofarads facilitates economical integration of the PLL onto an integrated circuit, and more particularly onto a field programmable gate array.
In some embodiments, the tap control at which the frequency lock condition occurred, and the value M used during frequency lock, are also used to determine a gain of the second phase detector. In some embodiments, a control block of the PLL determines this gain and then controls the gain of the second phase detector accordingly during the phase control step via a gain control signal. In some embodiments, time to lock is improved by using a higher gain of the second phase detector for an initial period of the phase lock step and then switching to a lower gain for the remainder of the phase lock step.
Other structures and methods are disclosed in the detailed description below. This summary does not purport to define the invention. The invention is defined by the claims.